The present invention concerns the control of throughput performance of floating point units.
Because of the complexity of mathematical calculations on non-integers, many computer systems have special processors devoted to making floating point calculations. Typically in such a computer system, when an instruction calls for a floating point operation, a floating point unit will perform the operation and present the result to the system (main) processor.
There are various cases where it is desirable to intentionally degrade performance of computer systems. For example, in order to satisfy certain U.S. export requirements for certain computer systems, it is necessary for the computer systems to perform below certain set criteria. One performance criteria used is the speed at which floating point calculations are performed.
It is desirable, therefore, under certain situations to be able to slow the operation of floating point units. In most prior art systems, a floating point co-processor has existed on a separate chip than the central processor. See, for example, Donald Steiss, et al., A 65 MHz Floating-Point Coprocessor for a RISC Processor, ISSCCY1/Session 5/Microprocessors/Paper TA 5.3, 1991 IEEE International Solid-State Circuits Conference, p. 94. In such a case, several options exist to limit computer system performance. For example, in many cases, the floating point co-processor can be eliminated entirely. Alternately, the clock signals or control signals to the floating point co-processor can be slowed in order to degrade the throughput of floating point operations.
In some more recently developed computer systems, however, floating point capability is incorporated on the same chip that houses the main processor. See for example, Eric DeLano, et al., A High Speed Superscalar PA-RISC. Processor, IEEE COMPCON, 1992, (0-8186-2655-0/92) pp. 116-120. In such a computer system, prior methods to slow operation of the computer system may be inconvenient, not feasible, or expensive. For example, elimination of the floating point unit from certain chips may entail significant special design and manufacturing costs. Slowing the clock to the chip in order to slow floating point operation may seriously degrade performance in non-floating point operations.